Digital-Design-and-Computer-Architecture-第五章归纳

0 前言

这一章学习了小数的二进制表示，一些更复杂的blocks，对之前的很多内容做了拓展和补充。

1 Number Systems

Fixed-Point Number

Fixed-point notation has an implied binary point between the integer and fraction bits, analogous to the decimal point between the integer and fraction digits of an ordinary decimal number.

There is no way of knowing the existence of the binary point except through agreement of those people interpreting the number.

Floating-Point Number Systems

Sign: 0+, 1-.

Biased Exponent: Original exponent +127. (32bit)

Fraction: The first bit of mantissa is erased.

Special Cases

Formats

Rounding

The rounding modes are: round down, round up, round toward zero, and round to nearest. The default rounding mode is round to nearest.

A number overflows to $\pm \infty$ when its magnitude is too large to be represented. Likewise, a number underflows to $0$ when it is too tiny to be represented.

Floating-Point Addition

1. Extract exponent and fraction bits.
2. Prepend leading 1 to form the mantissa.
3. Compare exponents.
4. Shift smaller mantissa if necessary.
5. Add mantissas.
6. Normalize mantissa and adjust exponent if necessary.
7. Round result.
8. Assemble exponent and fraction back into floating-point number.

2 Arithmetic Circuits

Addition

Half Adder

Full Adder

Ripple Carry Adder

Carry Lookahead Adder (CLA)

$$
G_i=A_iB_i\
P_i=A_i+B_i\
C_i=G_i+P_iC_{i-1}
$$

As for multiple-bit occasions,
$$
G_{i:j}=C_i\
P_{i:j}=\prod_{k=i}^jP_k\
C_{i:j}=G_{i:j}+P_{i:j}C_{in}
$$

Prefix Adder

They first compute G and P for pairs of columns, then for blocks of 4, then for blocks of 8, then 16, and so forth until the generate signal for every column is known. The sums are computed from these generate signals.

Subtraction

Subtraction is almost as easy: flip the sign of the second number, then add.

Comparators

Equality Comparator

Magnitude Comparator

Magnitude comparison is usually done by computing A − B and looking at the sign (most significant bit) of the result as shown in Figure 5.12.

Arithmetic/Logical Unit (ALU)

Shifters

Multiplication

Division

略

3 Sequential Building Blocks

Counter

module counter #(parameter N=8)
    		   (input clk, rst
                output [N-1:0] q);
    always@(posedge clk,posedge rst) begin
        if (rst) q<=4'b0000;
        else q<=q+1;
    end
endmodule

Shift Register

module shiftReg #(parameter N=8)
    (input [N-1:0]d,
     input clk,load,rst,sin,
     output [N-1:0] q,
     output sout)
    always@(posedge clk,posedge rst) begin
        if(rst) q<=0;
        else if(load) q<=d;
        else q<={q[N-2:0],sin};
    end
    assign sout=q[N-1];
endmodule

Scan Chains

4 Memory Arrays

Memories are classified based on how they store bits in the bit cell. The broadest classification is random access memory (RAM) versus read only memory (ROM). RAM is volatile, meaning that it loses its data when the power is turned off. ROM is nonvolatile, meaning that it retains its data indefinitely, even without a power source.

RAM and ROM received their names for historical reasons that are no longer very meaningful.

DRAM

SRAM

ROM

module RAM #(parameter N=6, M=32)
    (input clk, we,
     input [M-1:0] adr,din,
     output [M-1:0] dout)
    reg [M-1:0] mem [2**N-1:0];
    always@(posedge clk) begin
        if(we) mem[adr]<=din;
    end
    assign dout=mem[adr];
endmodule

PROM

Fuse-programmable ROM

Memory arrays used to perform logic are called lookup tables (LUTs).

5 Logic Arrays

PLA

FPGA

FPGAs are built as an array of configurable logic elements (LEs), also referred to as configurable logic blocks (CLBs). Each LE can be configured to perform combinational or sequential functions.

The LEs are surrounded by input/output elements (IOEs) for interfacing with the outside world.

6 Array Implementations

Refer to Chapter 1.